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      1. 專注電子技術學習與研究
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        JLink、JTAG接口詳細圖解

        作者:佚名   來源:本站原創   點擊數:  更新時間:2014年08月18日   【字體:

         


        說明:

        1腳:通常連接到目標板的vdd,用來檢測目標系統是否供電;檢測原理上圖中有簡單的說明。

        2腳:原版的JLink這個引腳沒有使用,不提供Vsupply輸出,而很多改造版的JLink通過跳線選擇從該引腳輸出3.3V的電壓給外邊,我的就是這樣的。

        可以到網上找JLink的原理圖看看。

        http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0517b/Cjaeccji.html

        JTAG interface signals

        The following table describes the signals on the JTAG interfaces:

        Table 1. JTAG signals

        Signal

        I/O

        Description

        DBGACK

        -

        This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug acknowledge signal from the target system. It is recommended that this signal is pulled LOW on the target.

        DBGRQ

        -

        This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. The RVI software maintains this signal as LOW.

        When applicable,RVI uses the scan chain 2 of the processor to put the processor in debug state. It is recommended that this signal is pulled LOW on the target.

        GND

        -

        Ground.

        nSRST

        Input/output

        Active Low output from RVI to the target system reset, with a 4.7kΩ pull-up resistor for de-asserted state. This is also an input to RVI so that a reset initiated on the target can be reported to the debugger.

        This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.

        nTRST

        Output

        Active Low output from RVI to the Reset signal on the target JTAG port, driven to the VTref voltage for de-asserted state. This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.

        RTCK

        Input

        Return Test Clock signal from the target JTAG port to RVI. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. RVI provides Adaptive Clock Timing, that waits for TCK changes to be echoed correctly before making more changes. Targets that do not have to process TCK can ground this pin.

        RTCK is not supported in Serial Wire Debug (SWD) mode.

        TCK

        Output

        Test Clock signal from RVI to the target JTAG port. It is recommended that this pin is pulled LOW on the target.

        TDI

        Output

        Test Data In signal from RVI to the target JTAG port. It is recommended that this pin is pulled HIGH on the target.

        TDO

        Input

        Test Data Out from the target JTAG port to RVI. It is recommended that this pin is pulled HIGH on the target.

        TMS

        Output

        Test Mode signal from RVI to the target JTAG port. This pin must be pulled HIGH on the target so that the effect of any spurious TCKs when there is no connection is benign.

        Vsupply

        Input

        This pin is not connected in the RVI unit. It is reserved for compatibility with other equipment to be used as a power feed from the target system.

        VTref

        Input

        This is the target reference voltage. It indicates that the target has power, and It must be at least 0.628V. VTref is normally fed from Vdd on the target hardware and might have a series resistor (though this is not recommended). There is a 10kΩ pull-down resistor on VTref in RVI. 

        ARM系統的JTAG接口的設計不當往往使硬件系統無法調試,所以在設計ARM系統前要先熟悉ARM系統的JTAG接口的定義和常見問題。
         
        1.ARM系統的JTAG接口是如何定義的? 每個PIN又是如何連接的?
        下圖是JTAG接口的信號排列示意:
        接口是一個20腳的IDC插座。下表給出了具體的信號說明:
        表 1 JTAG引腳說明
        序號
        信號名
        方向
        說 明
        1
        Vref
        Input
        接口電平參考電壓,通?芍苯咏与娫
        2
        Vsupply
        Input
        電源
        3
        nTRST
        Output
        (可選項) JTAG復位。在目標端應加適當的上拉電阻以防止誤觸發。
        4
        GND
        --
        接地
        5
        TDI
        Output
        Test Data In from Dragon-ICE to target.
        6
        GND
        --
        接地
        7
        TMS
        Output
        Test Mode Select
        8
        GND
        --
        接地
        9
        TCK
        Output
        Test Clock output from Dragon-ICE to the target
        10
        GND
        --
        接地
        11
        RTCK
        Input
        (可選項) Return Test Clock。由目標端反饋給Dragon-ICE的時鐘信號,用來同步TCK信號的產生。不使用時可以直接接地。
        12
        GND
        --
        接地
        13
        TDO
        Input
        Test Data Out from target to Dragon-ICE.
        14
        GND
        --
        接地
        15
        nSRST
        Input/Output
        (可選項) System Reset,與目標板上的系統復位信號相連?梢灾苯訉δ繕讼到y復位,同時可以檢測目標系統的復位情況。為了防止誤觸發,應在目標端加上適當的上拉電阻。
        16
        GND
        --
        接地
        17
        NC
         
        保留
        18
        GND
        --
        接地
        19
        NC
        --
        保留
        20
        GND
        --
        接地
         
        2.目標系統如何設計?
          目標板使用與Dragon-ICE一樣的20腳針座,信號排列見表1。RTCK和 nTRST這兩個信號根據目標ASIC有否提供對應的引腳來選用。nSRST則根據目標系統的設計考慮來選擇使用。下面是一個典型的連接關系圖:
          
          復位電路中可以根據不同的需要包含上電復位、手動復位等等功能。如果用戶希望系統復位信號nSRST能同時觸發JTAG口的復位信號nTRST,則可以使用一些簡單的組合邏輯電路來達到要求。后面給出了一種電路方案的效果圖。
         
                     圖 3 一個復位電路結構的例子

          在目標系統的PCB設計中,最好把JTAG接口放置得離目標ASIC近一些,如果這兩者之間的連線過長,會影響JTAG口的通信速率。
        另外電源的連線也需要加以額外考慮,因為Dragon-ICE要從目標板上吸取超過100mA的大電流。最好能有專門的敷銅層來供電,假如只能使用連線供電的話,最小線寬不應小于10mil (0.254mm)。
         
        3. 14腳JTAG如何與20JTAG連接?
          Dragon-ICE使用工業標準的20腳JTAG插頭,但是有些老的系統采用一種14腳的插座
        。這兩類接口的信號排列如下:
          這兩類接口之間的信號電氣特性都是一樣的,因此可以把對應的信號直接連起來進
        行轉接。Dragon-ICE配備這種轉接卡,隨機配備。

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